An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells that perform logical functions on input signals. A set of block connectors are used to provide connectability between cells and accessibility to a hierarchical...http://www.google.fr/patents/US6989688?utm_source=gb-gplus-shareBrevet US6989688 - Architecture and interconnect scheme for programmable logic circuits
Architecture and interconnect scheme for programmable logic circuits
