A refresh control circuit is provide for a pseudo SRAM that includes a plurality of banks. The refresh control circuit includes a buffer enable control unit that outputs a chip select internal control signal, and a bank selection unit that generates a single bank select signal or an all-bank select signal...http://www.google.fr/patents/US7336555?utm_source=gb-gplus-shareBrevet US7336555 - Refresh control circuit of pseudo SRAM
