A processor having a reduction unit that sums m input operands plus an accumulator value, with the option of saturating after each addition or wrapping around the result of each addition. The reduction unit also allows the m input operands to be subtracted from the accumulator value by simply inverting...http://www.google.fr/patents/US7593978?utm_source=gb-gplus-shareBrevet US7593978 - Processor reduction unit for accumulation of multiple operands with or without saturation
Processor reduction unit for accumulation of multiple operands with or ...
