Reduced-size LDMOS transistor having reduced leakage and a reduced propensity to latch-up. The LDMOS transistor has a trench with vertical sidewalls adjacent to a source region to help reduce a vertical projective area of the source region....http://www.google.fr/patents/US5508547?utm_source=gb-gplus-shareBrevet US5508547 - LDMOS transistor with reduced projective area of source region
LDMOS transistor with reduced projective area of source region
