A processing system comprising: i) a processor core; ii) a memory; iii) a plurality of peripheral devices; and iv) a communication bus coupled to the processor core, the memory and the peripheral devices for transferring bus transactions between the processor core, the memory, and the peripheral devices....http://www.google.fr/patents/US7143225?utm_source=gb-gplus-shareBrevet US7143225 - Apparatus and method for viewing data processor bus transactions on address pins during memory idle cycles
Apparatus and method for viewing data processor bus transactions on address ...
