A non-blocking load buffer for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects...http://www.google.fr/patents/US5812799?utm_source=gb-gplus-shareBrevet US5812799 - Non-blocking load buffer and a multiple-priority memory system for real-time multiprocessing
Non-blocking load buffer and a multiple-priority memory system for real-time ...
