A method and apparatus for determining the layout of an integrated circuit, in accordance with timing constraints, by means of sizing the buffers in the layout. A nominal netlist for the layout of the integrated circuit is used to determine critical paths through the circuit. The time-critical paths...http://www.google.fr/patents/US5654898?utm_source=gb-gplus-shareBrevet US5654898 - Timing-driven integrated circuit layout through device sizing
Timing-driven integrated circuit layout through device sizing
