An interlock circuit is set forth which provides for controlling asynchronous data transfers between a host processor and a plurality of microprocessors via a common buffer. The interlock circuit consists of an interconnection of latches arranged so that the first processor initiating a transfer request...http://www.google.fr/patents/US4244018?utm_source=gb-gplus-shareBrevet US4244018 - Interlock control of asynchronous data transmission between a host processor and a plurality of microprocessors through a common buffer
Interlock control of asynchronous data transmission between a host processor ...
