A method and system are disclosed for reducing run-time delay during conditional branch instruction execution in a pipelined processor system. A series of queued sequential instructions and conditional branch instructions are processed wherein each conditional branch instruction specifies...http://www.google.fr/patents/US5784604?utm_source=gb-gplus-shareBrevet US5784604 - Method and system for reduced run-time delay during conditional branch execution in pipelined processor systems utilizing selectively delayed sequential instruction purging
Method and system for reduced run-time delay during conditional branch ...
