A digital dynamic circuit is presented which effectively extends the percentage of each clock cycle available for logical operations. The circuit uses a two-phase overlapping clocking design which results in the circuit (1) having only a single latch delay, (2) being insensitive to mid-cycle clock jitter,...http://www.google.fr/patents/US5504441?utm_source=gb-gplus-shareBrevet US5504441 - Two-phase overlapping clocking technique for digital dynamic circuits
Two-phase overlapping clocking technique for digital dynamic circuits
