An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required...http://www.google.fr/patents/US20030067817?utm_source=gb-gplus-shareBrevet US20030067817 - Distributed write data drivers for burst access memories
Distributed write data drivers for burst access memories
