A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units...http://www.google.fr/patents/US6128711?utm_source=gb-gplus-shareBrevet US6128711 - Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes
Performance optimization and system bus duty cycle reduction by I/O bridge ...
