A high-density folded bitline memory array architecture is disclosed. High memory cell packing density is achieved by dividing polysilicon wordlines into short individual segments in the folded bitline scheme. Each wordline segment forms the gate of one or two DRAM memory cell transistors, and each segment...http://www.google.fr/patents/US6826069?utm_source=gb-gplus-shareBrevet US6826069 - Interleaved wordline architecture
