An apparatus and method implementing an algorithm for determining the most likely least recently used cache line in a cache so that this cache line can be written back to main memory. This algorithm is implemented on a bus control unit bridging a 50 Mhz multi-processor interconnect bus with a 33 Mhz...http://www.google.fr/patents/US5594886?utm_source=gb-gplus-shareBrevet US5594886 - Pseudo-LRU cache memory replacement method and apparatus utilizing nodes
Pseudo-LRU cache memory replacement method and apparatus utilizing nodes
