A cache memory uses at least two synchronous memory devices operable of responding to an external clock signal and performing a bank operation mode. The memory device includes a control logic for generating an informing signal denoting a non-selection of the memory device, the informing signal responding...http://www.google.fr/patents/US5963503?utm_source=gb-gplus-shareBrevet US5963503 - Synchronous systems having secondary caches
