A circuit is designed with a first register circuit (364) arranged to store a state matrix. A memory circuit (710) is arranged to store a plurality of addressable matrices. A control circuit (700) is coupled to receive a delay value and a clock signal. The control circuit is arranged to address a selected...http://www.google.fr/patents/US6687376?utm_source=gb-gplus-shareBrevet US6687376 - High-speed long code generation with arbitrary delay
High-speed long code generation with arbitrary delay
