A communication receiver (100) employs a discrete time digital phase locked loop (142) for maintaining a generated signal (144) locked to a reference signal (136). The discrete time digital phase locked loop (142) includes a phase detector (202), an accumulator (219), an adder (227), and a controlled...http://www.google.fr/patents/US5576664?utm_source=gb-gplus-shareBrevet US5576664 - Discrete time digital phase locked loop
