The invention relates to an FPGA (field programmable gate array) with a plurality of functional blocks. An interface enables data and address communication between a processor and the FPGA. The gate array is provided with configurations from a configuration memory. The FPGA also includes a buffer memory...http://www.google.fr/patents/US20020125911?utm_source=gb-gplus-shareBrevet US20020125911 - Reconfigurable gate array
Numéro de demande: 10/112,532 Numéro de publication: US 2002/0125911 A1 Date de dépôt: 28 mars 2002 Brevet délivré: US6717436 ( Date de délivrance 6 avr. 2004)
