A serializer/deserializer for a flow of n-bits of data shifted according to the rate of a clock includes an n-rows and n-columns matrix of 1-bit registers (00-77). Each 1-bit register is connected through its input to a first switch connected to the output of the register in the same row and lower rank...http://www.google.fr/patents/US5101202?utm_source=gb-gplus-shareBrevet US5101202 - Serializer/deserializer with a triangular matrix
