A pulsed circuit topology including a pulsed domino flip-flop. A circuit includes a domino logic gate having a domino output node responsive to input data during an evaluate pulse. Reset circuitry initiates and self-terminates a reset pulse during which the domino output node is precharged. A latch responsive...http://www.google.fr/patents/US6496038?utm_source=gb-gplus-shareBrevet US6496038 - Pulsed circuit topology including a pulsed, domino flip-flop
Pulsed circuit topology including a pulsed, domino flip-flop
