The load/sense control of the setting value that corresponds to the processor core for CMP, etc. processors that have multi-cores realize, for such processors with multi-core structures, the shortening of system boot time during multi-core operation, flexible debugging methods, and improvement of yield...http://www.google.fr/patents/US20050289286?utm_source=gb-gplus-shareBrevet US20050289286 - Multi-core processor control method
