A buffer amplifier architecture for buffering signals which are supplied in parallel to identical chips, particularly DRAM chips, on a semiconductor memory module, is disclosed. The architecture has adjustable delay circuits in each signal line and a delay detector circuit which receives a clock signal...http://www.google.fr/patents/US6894933?utm_source=gb-gplus-shareBrevet US6894933 - Buffer amplifier architecture for semiconductor memory circuits
Buffer amplifier architecture for semiconductor memory circuits
