A content addressable memory employs a word-sliced architecture, in order to localize word match logic, and a global data bus, to convey data between the memory input/output circuitry and the plurality of word slices. Timing information is embedded in the global data bus in the form of a model global...http://www.google.fr/patents/US5943252?utm_source=gb-gplus-shareBrevet US5943252 - Content addressable memory
