A data processing apparatus includes an arithmetic logic unit is divided into a plurality of sections. Each section generates at a corresponding output a digital resultant signal representing a combination of respective subsets of first and second multibit digital inputs. The arithmetic logic unit includes...http://www.google.fr/patents/US5592405?utm_source=gb-gplus-shareBrevet US5592405 - Multiple operations employing divided arithmetic logic unit and multiple flags register
Multiple operations employing divided arithmetic logic unit and multiple ...
