A non-volatile memory cell structure which includes a floating gate, a reverse breakdown element and a read transistor. The reverse breakdown element is at least partially formed in a first region of a first conductivity type in a semiconductor substrate, and underlies a portion of the floating gate;...http://www.google.fr/patents/US6215700?utm_source=gb-gplus-shareBrevet US6215700 - PMOS avalanche programmed floating gate memory cell structure
