A plurality of testing circuits formed of parallel registers are incorporated in a plurality of circuit portions constituting a data processing circuit, the circuit portions having different number of bits to be processed. Each parallel register comprises scan latch circuits and latch circuits. The sum...http://www.google.fr/patents/US4913557?utm_source=gb-gplus-shareBrevet US4913557 - Intergrated logic circuit having testing function circuit formed integrally therewith
Intergrated logic circuit having testing function circuit formed integrally ...
