An apparatus comprising a plurality of first counters, a second counter, and a logic circuit. The plurality of first counters may each be configured to increment a first value in response to receiving one of a plurality of incoming data packets on an associated port. The second counter may be configured...http://www.google.fr/patents/US7257080?utm_source=gb-gplus-shareBrevet US7257080 - Dynamic traffic-based packet analysis for flow control
Dynamic traffic-based packet analysis for flow control
