A non-volatile memory is described which includes an array of memory cells arranged in rows and columns. A split source line architecture is implemented and uses isolation transistors located throughout the memory array to couple selected memory cells in response to an active row line signal. The isolation...http://www.google.fr/patents/US20020044483?utm_source=gb-gplus-shareBrevet US20020044483 - Flash memory with overerase protection
Numéro de demande: 09/940,979 Numéro de publication: US 2002/0044483 A1 Date de dépôt: 28 août 2001 Brevet délivré: US6442066 ( Date de délivrance 27 août 2002)
