Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as including a number...http://www.google.fr/patents/US8000136?utm_source=gb-gplus-shareBrevet US8000136 - Non-volatile memory with both single and multiple level cells
Non-volatile memory with both single and multiple level cells
