A digital clock recovery circuit is presented which uses a delay line to produce a plurality of delayed sample signals. The sample signals are used to sample incoming data in a phase detector and the resultant sampled data is then resampled by the tentatively correct apparatus clock output signal. The...http://www.google.fr/patents/US4819251?utm_source=gb-gplus-shareBrevet US4819251 - High speed non-return-to-zero digital clock recovery apparatus
High speed non-return-to-zero digital clock recovery apparatus
