A serial communication circuit which is so configured that the sub CPU SC determines a timing of bit formats with software, specificially, that the sub CPU SC controls a level of each section or an output timing of each signal of one unit to be transmitted of data by writing specific values with software...http://www.google.fr/patents/US5590371?utm_source=gb-gplus-shareBrevet US5590371 - Serial communication circuit on an LSI chip and communicating with another microcomputer on the chip
Serial communication circuit on an LSI chip and communicating with another ...
