A processing system includes circuitry and methodology for selecting clock generation modes between phase-locked loop and static delay line loop circuitries. The node may be selectable through an externally accessible pin, an internal bond wire option, a boundary test scan control point, or other programmable...http://www.google.fr/patents/US5926053?utm_source=gb-gplus-shareBrevet US5926053 - Selectable clock generation mode
