An apparatus and method for performing enhanced algorithmic processing, including reduced cycle-count fast Fourier transform (FFT) calculations. In one aspect, the invention comprises a user-configurable processor having an extension instruction adapted for reduced cycle-count algorithmic operations....http://www.google.fr/patents/US7010558?utm_source=gb-gplus-shareBrevet US7010558 - Data processor with enhanced instruction execution and method
Data processor with enhanced instruction execution and method
