A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices organized into a set of nodes supported by a node...http://www.google.fr/patents/US6457085?utm_source=gb-gplus-shareBrevet US6457085 - Method and system for data bus latency reduction using transfer size prediction for split bus designs
Method and system for data bus latency reduction using transfer size ...
