A multi-access method which is applied to a cache memory device interposed between a processor and a storage device, for enabling multi-access. When two or more access requests are received, a plurality of pairs (each pair composed of a data array and a tag array) are divided into two or more non-overlapping...http://www.google.fr/patents/US6038647?utm_source=gb-gplus-shareBrevet US6038647 - Cache memory device and method for providing concurrent independent multiple accesses to different subsets within the device
Cache memory device and method for providing concurrent independent multiple ...
