A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including...http://www.google.fr/patents/US6438063?utm_source=gb-gplus-shareBrevet US6438063 - Integrated circuit memory devices having selectable column addressing and methods of operating same
Integrated circuit memory devices having selectable column addressing and ...
