A multi-phase clock generator is implemented by a delay circuit that receives an input clock signal. The clock generator couples the input clock signal to a first clock output terminal and to a delay circuit. The delay circuit delays the input clock signal to produce a delayed clock signal, and the delayed...http://www.google.fr/patents/US6029252?utm_source=gb-gplus-shareBrevet US6029252 - Method and apparatus for generating multi-phase clock signals, and circuitry, memory devices, and computer systems using same
Method and apparatus for generating multi-phase clock signals, and circuitry ...
