A multiple level routing architecture for a programmable logic device having logical blocks, each logical block comprising a plurality of cells, with a first level routing resources coupling the cells of logical blocks. A second level routing resources coupling the first level routing resources through...http://www.google.fr/patents/US20060114023?utm_source=gb-gplus-shareBrevet US20060114023 - Floor plan for scalable multiple level tab oriented interconnect architecture
Floor plan for scalable multiple level tab oriented interconnect architecture
Numéro de demande: 11/326,543 Numéro de publication: US 2006/0114023 A1 Date de dépôt: 4 janv. 2006 Brevet délivré: US7126375 ( Date de délivrance 24 oct. 2006)
