A plurality of processors on a chip is operated in lockstep. A crossbar switch on the chip couples and decouples the plurality of processors to a plurality of banks in a level-two (L2) cache. As data is stored in a first bank of the L2 cache, the old data at that location is passed through the crossbar...http://www.google.fr/patents/US7191292?utm_source=gb-gplus-shareBrevet US7191292 - Logging of level-two cache transactions into banks of the level-two cache for system rollback
Logging of level-two cache transactions into banks of the level-two cache ...
