A self timed memory address control circuit is described. A Y address signal is pre-decoded and then latched. Address transition detection circuits coupled to X and Y address lines output a pulse to an equalization circuit whenever one of the corresponding address signals change. The WEB address detection...http://www.google.fr/patents/US5940337?utm_source=gb-gplus-shareBrevet US5940337 - Method and apparatus for controlling memory address hold time
Method and apparatus for controlling memory address hold time
