An improved symbol synchronization circuit is provided for generting a clock signal in a receiver having an input signal comprising a stream of symbols at a symbol rate of f.sub.symbol. According to the invention, a correlator is provided that operates on a multiplicity (k) of multi-phase signals, .phi..sub.1...http://www.google.fr/patents/US5103465?utm_source=gb-gplus-shareBrevet US5103465 - Symbol synchronization circuit
