An address generation engine is disclosed for a digital video decoder unit coupled to memory in a digital video decoder system wherein the memory accommodates multi-format and/or reduced video data storage. The address generation engine includes a processor and address generation hardware. The processor,...http://www.google.fr/patents/US5963222?utm_source=gb-gplus-shareBrevet US5963222 - Multi-format reduced memory MPEG decoder with hybrid memory address generation
Multi-format reduced memory MPEG decoder with hybrid memory address generation
