A method for making an integrated circuit chip carrier having reduced and regulable interlead capacitance and reduced glass chip formation. The chip carrier includes a substrate having a central cavity for locating an integrated circuit die, an inner channel and an outer channel, adhesive glass located...http://www.google.fr/patents/US5369059?utm_source=gb-gplus-shareBrevet US5369059 - Method for constructing a reduced capacitance chip carrier
Method for constructing a reduced capacitance chip carrier
