In an address selecting circuitry for a semiconductor memory device including a matrix of memory cells arrayed in rows and columns, an address input signal A.sub.i for any given bit of address data is applied to a single address signal setting circuit to produce a set of two different logic signals a.sub.i...http://www.google.fr/patents/US4104733?utm_source=gb-gplus-shareBrevet US4104733 - Address selecting circuitry for semiconductor memory device
Address selecting circuitry for semiconductor memory device
