A method and apparatus for including in a processor instructions for performing integer transforms including multiply-add operations and horizontal-add operations on packed data. In one embodiment, a processor is coupled to a memory that stores a first packed byte data and a second packed byte data....http://www.google.fr/patents/US7624138?utm_source=gb-gplus-shareBrevet US7624138 - Method and apparatus for efficient integer transform
Method and apparatus for efficient integer transform
