An improved logic simulation machine in which non-unitary delays of logic functions being simulated are permitted and in which the delay time can be made different for low-to-high and high-to-low transitions. A plurality of basic processors are interconnected with a control processor through an inter-processor...http://www.google.fr/patents/US4656580?utm_source=gb-gplus-shareBrevet US4656580 - Logic simulation machine
