A write-through data cache which incorporates a line addressable locking mechanism. By executing a software lock instruction or unlock instruction, a microprocessor controls the locking or unlocking of individual cache lines in the data cache. A locked cache line is not subject to deallocation. By locking...http://www.google.fr/patents/US6092159?utm_source=gb-gplus-shareBrevet US6092159 - Implementation of configurable on-chip fast memory using the data cache RAM
Implementation of configurable on-chip fast memory using the data cache RAM
