A structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing...http://www.google.fr/patents/US6147535?utm_source=gb-gplus-shareBrevet US6147535 - Clock phase generator for controlling operation of a DRAM array
Clock phase generator for controlling operation of a DRAM array
