A technique and system for reading instruction data from a cache memory with minimum delays. Addresses are calculated and applied to the cache memory in two or more cycles by a pipelined address generation circuit. While data at one address is being retrieved, the next address is being calculated. It...http://www.google.fr/patents/US6223257?utm_source=gb-gplus-shareBrevet US6223257 - Instruction cache address generation technique having reduced delays in fetching missed data
Instruction cache address generation technique having reduced delays in ...
