Methods, circuits, processes, devices, and/or arrangements for a non-volatile memory (NVM) cell operable at relatively low voltages are disclosed. In one embodiment, an NVM cell can include: (i) a gate over a charge trapping layer, the charge trapping layer being insulated from the gate by a first insulating...http://www.google.fr/patents/US7969785?utm_source=gb-gplus-shareBrevet US7969785 - Low voltage non-volatile memory with charge trapping layer
Low voltage non-volatile memory with charge trapping layer
